FIG. 30 (see Patent Document 1) is a plan view of a conventional active matrix substrate. As shown in the figure, in each pixel area 750, its pixel electrode 751 is surrounded by a scanning signal line 752 for supplying a scanning signal- and a data signal line 753 for supplying a data signal, in such a manner that these signal lines intersect with one another. At the intersection of the scanning signal line 752 and the data signal line 753, a TFT (Thin Film Transistor) 754 is provided. The gate electrode 755 of the TFT 754 is connected to the scanning signal line 752, so that the TFT 754 is turned on/off in response to the supply of a scanning signal. The source electrode 766 of the TFT 754 is connected to the data signal line 753 and receives a data signal. The drain electrode 777 of the TFT 754 is connected to a drain lead line.
To prevent self-discharge of a liquid crystal layer when the TFT is turned off and to prevent the deterioration of an image signal due to an off-current of the TFT, the pixel area 750 is provided with a storage capacity wire 759 having, for example, a circular shape. As shown in FIG. 30, this storage capacity wire 759 is provided to overlap the edges of the pixel electrode 751. The drain electrode 777 of the TFT 754 is connected to the pixel electrode 751, and the pixel electrode 751 and the storage capacity wire 759 form a storage capacitor.
[Patent Document 1] Japanese Unexamined Patent Publication No. 6-301059 (published on Oct. 28, 1994)
[Patent Document 2] Japanese Unexamined Patent Publication No. 7-287252 (published on Oct. 31, 1995)
[Patent Document 3] Japanese Unexamined Patent Publication No. 2004-78157 (published on Mar. 11, 2004)
[Patent Document 4] Japanese Unexamined Patent Publication No. 6-332009 (published on Dec. 2, 1994)
[Patent Document 5] Japanese re-publication of PCT international application No. WO97/00463 (internationally published on Jan. 3, 1997)